A defined state,
and a rule for the
next one.
The architectural state of STRATA-16 is 312 bits: sixteen registers, an instruction register, a program counter, a stack pointer and four flags. Everything else the machine touches is store, and the store is not part of the processor.
Every instruction consumes a defined architectural state and produces a deterministic successor. Nothing is inferred between cycles, and no phase reads a value that the previous phase did not write.
- ADDER144
- LOGIC UNIT160
- BARREL SHIFTER256
- RESULT SELECT192
- FLAG UNIT52
- READ PORT A960
- READ PORT B960
- REGISTER FILE132
- COUNTER INCREMENT72
- COUNTER SOURCE96
- OPCODE DECODER261
- MEMORY PORT242
- STACK POINTER80
- INSTRUCTION REGISTER64
- CONTROL MATRIX241
3,912 NAND · 312 FF · 177 CONTROL ASSERTIONS ACROSS THE SET
| # | BLOCK | PC | OP | OPERANDS | RESULT | Φ | COMMITMENT |
|---|---|---|---|---|---|---|---|
| NO TRANSITIONS COMMITTED SINCE RESET | |||||||
| NO TRANSITIONS COMMITTED SINCE RESET | |||||||
| NO TRANSITIONS COMMITTED SINCE RESET | |||||||
| ADDR | 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | REGION |
|---|---|---|---|---|---|---|---|---|---|
| 000 | DATA | ||||||||
| 008 | |||||||||
| 010 | |||||||||
| 018 | |||||||||
| 020 | |||||||||
| 028 | |||||||||
| 030 | |||||||||
| 038 | |||||||||
| 040 | |||||||||
| 048 | |||||||||
| 050 | |||||||||
| 058 | |||||||||
| 060 | |||||||||
| 068 | |||||||||
| 070 | |||||||||
| 078 | |||||||||
| 080 | |||||||||
| 088 | |||||||||
| 090 | |||||||||
| 098 | |||||||||
| 0A0 | |||||||||
| 0A8 | |||||||||
| 0B0 | |||||||||
| 0B8 | |||||||||
| 0C0 | |||||||||
| 0C8 | |||||||||
| 0D0 | |||||||||
| 0D8 | |||||||||
| 0E0 | |||||||||
| 0E8 | |||||||||
| 0F0 | |||||||||
| 0F8 |
Counted, not
claimed.
The gate budget is a table of structure. Each block states how it decomposes into the primitive, using the cell costs the gate level model actually pays: NOT 1, AND 2, OR 3, XOR 4, MUX2 4, half adder 6, full adder 9.
Two sixteen-to-one read multiplexers dominate the budget at 1,920 cells. That is the price of a two-port register file with no gate but NAND, and it is left visible rather than amortised into a smaller figure.
| BLOCK | LAYER | NAND | FF | BUDGET | DERIVATION |
|---|---|---|---|---|---|
| ADDER | ARITHMETIC | 144 | — | 16 × full adder (9) | |
| LOGIC UNIT | ARITHMETIC | 160 | — | 16 × (AND 2 + OR 3 + XOR 4 + NOT 1) | |
| BARREL SHIFTER | ARITHMETIC | 256 | — | 4 stages × 16 × MUX2 (4) | |
| RESULT SELECT | ARITHMETIC | 192 | — | 16 × 4→1 MUX (3 × MUX2) | |
| FLAG UNIT | ARITHMETIC | 52 | 4 | Z: 15 × OR (3) + NOT (1) = 46 · N C V: 6 · 4 flip-flops | |
| READ PORT A | REGISTERS | 960 | — | 16 × 16→1 MUX (15 × MUX2 = 60) | |
| READ PORT B | REGISTERS | 960 | — | 16 × 16→1 MUX (15 × MUX2 = 60) | |
| REGISTER FILE | REGISTERS | 132 | 256 | 16 × AND4 (6) + 4 × NOT + 16 × AND2 (2) · 16 × 16 flip-flops | |
| COUNTER INCREMENT | CONTROL | 72 | 12 | 12 × half adder (6) · 12 flip-flops | |
| COUNTER SOURCE | CONTROL | 96 | — | 2 × (12 × MUX2) | |
| OPCODE DECODER | CONTROL | 261 | — | 32 × AND5 (8) + 5 × NOT | |
| MEMORY PORT | MEMORY | 242 | — | address 3→1 MUX 96 · word assembly 64 · port compare 82 | |
| STACK POINTER | MEMORY | 80 | 8 | 8 × half adder (6) + 8 × MUX2 · 8 flip-flops | |
| INSTRUCTION REGISTER | CONTROL | 64 | 32 | 32 × AND2 (2) load enable · 32 flip-flops | |
| CONTROL MATRIX | CONTROL | 241 | — | 24 control terms × 3 × OR (3) = 216 · 5 phase lines × AND2 = 10 · 15 glue |
| ELEMENT | WIDTH | FF |
|---|---|---|
| REGISTER FILE | 16 × 16 | 256 |
| INSTRUCTION REGISTER | 32 bit | 32 |
| PROGRAM COUNTER | 12 bit | 12 |
| STACK POINTER | 8 bit page offset | 8 |
| FLAGS | Z N C V | 4 |
| TOTAL | architectural state | 312 |
- IR_LDINSTRUCTION REGISTER LOAD
- PC_INCPROGRAM COUNTER INCREMENT
- PC_LOADPROGRAM COUNTER LOAD
- RAREGISTER READ PORT A
- RBREGISTER READ PORT B
- IMM_SELIMMEDIATE SELECT
- ALU_ENARITHMETIC UNIT ENABLE
- SH_ENSHIFTER ENABLE
- FLG_WRFLAG WRITE
- REG_WRREGISTER WRITE
- MEM_RDMEMORY READ
- MEM_WRMEMORY WRITE
- SP_DECSTACK POINTER DECREMENT
- SP_INCSTACK POINTER INCREMENT
- HALT_LHALT LATCH
An address here
is not anonymous.
The store is byte addressed and accessed sixteen bits at a time, little endian. The top of it is not general: a stack page, a reserved region that reads zero, and two byte-wide ports that are the machine’s entire boundary with anything outside it.
Each port occupies a whole word so that a sixteen-bit access reads or writes a port without masking. The upper byte of a port word reads zero and ignores writes, which is why the reference programs load a port straight into a register.
| REGION | FROM | TO | BYTES | NOTE |
|---|---|---|---|---|
| DATA | 0x000 | 0xEFF | 3,840 | general read/write |
| STACK | 0xF00 | 0xF7F | 128 | 64 words, full descending |
| RESERVED | 0xF80 | 0xFFB | 124 | reads 0x00, writes ignored |
| PORT IN | 0xFFC | 0xFFD | 2 | host → machine, 1 byte |
| PORT OUT | 0xFFE | 0xFFF | 2 | machine → host, 1 byte |