ARRAY is a deterministic 16-bit processor composed from a single computational primitive. It advances one step per block, and every state transition is committed to the chain.
The contract does not emulate the processor. It executes the machine. Every cycle is a real state transition, and nothing is inferred between cycles.
No contract is deployed. Every figure on this page is read from the machine running in this browser, and the figures that describe a deployed instance are marked.
3,912 NAND · 312 FF · 177 CONTROL ASSERTIONS ACROSS THE SET
| # | BLOCK | PC | OP | OPERANDS | RESULT | Φ | COMMITMENT |
|---|---|---|---|---|---|---|---|
| NO TRANSITIONS COMMITTED SINCE RESET | |||||||
| NO TRANSITIONS COMMITTED SINCE RESET | |||||||
| NO TRANSITIONS COMMITTED SINCE RESET | |||||||
A machine is not a claim about capability. It is a data path, a store, a set of instructions and a boundary. Each of the four statements below corresponds to something in the netlist, and each figure beside it was produced by running the machine.
Nothing here is rounded for effect. Where a figure is a range, it is because the machine takes a different number of phases depending on what the flags say.
The machine consumes an input and follows a deterministic execution path. A comparison writes the flags, and the branch that follows consumes them. The path taken is a function of the state, not of timing.
A complete sixteen-bit arithmetic unit executes the fixed instruction set: one ripple carry adder, one bitwise logic unit, one four stage barrel shifter, and one result multiplexer. Subtraction is addition of the complement.
Sixteen registers and 4 KB of persistent store retain state across transitions, including a 64-word stack page for call depth. State survives a halt: a stopped machine is still readable.
The machine exposes an input and output boundary that lets programs interact with external state. There are no I/O instructions: both ports are mapped into the top of the store, so a load is a read and a store is a write.
Every part of the machine is built from a single computational primitive. Nothing is assumed and nothing is hidden: the processor is constructed in layers, from boolean logic to a verifiable state machine, and each layer is countable in terms of the layer below it.
NAND is universal, so no second kind of gate is required anywhere above it. The cost of that decision is visible in the budget: two read ports account for 1,920 of the 3,912 cells, because a sixteen-to-one multiplexer is expensive when it is made of nothing but NAND.
VIEW THE BUILD PROCESSOne two-input cell whose output is low only when both inputs are high. Every gate in the machine — inverter, conjunction, disjunction, exclusive disjunction, multiplexer, latch — is composed from it.
Sixteen full adders in a ripple carry chain. The carry out of bit fifteen is the carry flag; overflow is that carry differing from the carry into bit fifteen. Both flags come off the chain, not out of a formula.
The processor layer is the whole netlist, not a block of its own. Sequential elements are counted separately because a flip-flop is not a gate: it is a state element built from gates that holds a value between two edges of an external clock.
The opcode field is five bits wide, producing thirty-two possible instructions. All thirty-two are defined, so the set is closed: there is no reserved space, no extension mechanism, and no undefined opcode for a program to reach. The architecture is fixed. Programs are data.
Two omissions are deliberate. There is no SWAP, because three exclusive disjunctions exchange two registers without a temporary. There are no input or output instructions, because both ports are mapped into the store and a load already reads.
This is the ARRAY-16 R0 architecture specification. It is implemented by the machine in this page and by the independent model used in CHECK 02. It is not a deployed instruction set.
VIEW THE OPCODESA word is canonical when the seven reserved bits are zero and every field the instruction does not read is zero. Exactly one encoding exists for any instruction, which is what makes one machine’s transition comparable with another’s without a normalisation step. A non-canonical word raises a fault at fetch.
| OPCODE | HEX | MNEMONIC | OPERANDS | FLAGS | Φ |
|---|---|---|---|---|---|
| 00000 | 00 | — | — | 3 | |
| 00001 | 01 | Rd, Rs | — | 4 | |
| 00010 | 02 | Rd, #imm | — | 4 | |
| 00011 | 03 | Rd, [addr] | — | 5 | |
| 00100 | 04 | Rd, [Rs] | — | 5 | |
| 00101 | 05 | [addr], Rs | — | 5 | |
| 00110 | 06 | [Rd], Rs | — | 5 | |
| 00111 | 07 | Rs | — | 5 | |
| 01000 | 08 | Rd | — | 5 | |
| 01001 | 09 | Rd, Rs | ZNCV | 5 | |
| 01010 | 0A | Rd, #imm | ZNCV | 5 | |
| 01011 | 0B | Rd, Rs | ZNCV | 5 | |
| 01100 | 0C | Rd, #imm | ZNCV | 5 | |
| 01101 | 0D | Rd | ZNCV | 5 | |
| 01110 | 0E | Rd | ZNCV | 5 | |
| 01111 | 0F | Rd | ZNCV | 5 | |
| 10000 | 10 | Rd, Rs | ZN | 5 | |
| 10001 | 11 | Rd, Rs | ZN | 5 | |
| 10010 | 12 | Rd, Rs | ZN | 5 | |
| 10011 | 13 | Rd | ZN | 5 | |
| 10100 | 14 | Rd, #n | ZNC | 5 | |
| 10101 | 15 | Rd, #n | ZNC | 5 | |
| 10110 | 16 | Rd, #n | ZNC | 5 | |
| 10111 | 17 | Rd, Rs | ZNCV | 5 | |
| 11000 | 18 | Rd, #imm | ZNCV | 5 | |
| 11001 | 19 | addr | — | 5 | |
| 11010 | 1A | addr | — | 5 | |
| 11011 | 1B | addr | — | 5 | |
| 11100 | 1C | addr | — | 5 | |
| 11101 | 1D | addr | — | 5 | |
| 11110 | 1E | — | — | 5 | |
| 11111 | 1F | — | — | 3 |
Adds the source register to the destination register.
5 PHASES
UNLISTED FLAGS RETAIN THEIR VALUE
The arithmetic is checked against the same arithmetic built out of the primitive. The machine is checked against a second interpreter that shares no execution code with it. The encoding is checked by disassembling a word and reassembling the text. Randomised execution is checked for architectural validity at every phase. And the replay property the contract would depend on is checked by running the same program twice.
The fifth exists because a machine that agrees with itself is not evidence. It compares the sequence of state commitments produced by two independently constructed machines running the same program with the same inputs, digit for digit.
No third party has audited anything. Every figure below is produced by code in this page: a full CHECK 01 sweep runs 1,048,576 vectors through the machine and compares each one against the gate level model.
READ THE VERIFICATIONEvery arithmetic, logic and shift instruction produces the same result and the same four flags as the same operation built out of the primitive.
QUICK 4,096 · FULL 1,048,576 VECTORS
A second interpreter, sharing no execution code with the machine, reaches identical architectural state after every retired instruction.
QUICK 20,000 · FULL 400,000 RETIREMENTS
The encoding is canonical and the text path is closed: an instruction word disassembles to text that reassembles to the identical word.
QUICK 8,192 · FULL 131,072 WORDS
Randomised execution never reaches an undefined architectural state. It either runs, halts, or raises one of the declared faults.
QUICK 60,000 · FULL 1,200,000 PHASES
A machine replayed from its program and its inputs produces the identical sequence of state commitments. This is the property the contract requires.
QUICK 8,000 · FULL 120,000 COMMITMENTS
Every machine is an instance of the ARRAY-16 architecture with its own program memory and its own persistent execution state. The architecture is not a parameter: two instances differ only in what is in ROM and how far they have executed.
An instance identity is derived, not allocated. It is a digest of the name and the encoded program, so the same inputs always produce the same machine id, and a genesis commitment is taken from the machine with that program installed at cycle zero.
Records are written to this browser’s local storage. No transaction is sent and no contract is called, because no ARRAY contract is deployed.
OPEN THE FACTORYReads a word from RAM, adds a constant, writes it back, and repeats. The canonical resident program.
FIXED · NOT CONFIGURABLE
FIXED IN R0
The clock keeps supplying edges until the program halts or faults.
The identity is a digest of the name and the encoded program, so the same inputs always produce the same machine id. A deployed factory would write this record and the program words to a contract; this one writes them to your browser.
| MACHINE ID | NAME | PROGRAM | WORDS | MODE | CREATED | |
|---|---|---|---|---|---|---|
| NO INSTANCES. INITIALIZE ONE ABOVE. | ||||||
No ARRAY contract is deployed. Execution balance is undefined because nothing is charged for a transition that happens in your browser.
A committed transition is a block, an instruction, and the commitment that followed it. The explorer lists them in order and lets you inspect the architectural state at any one of them.
That state is not stored anywhere. It is recomputed by replaying the program from cycle zero to the selected cycle, which is why the commitment is worth keeping: it is the only thing a verifier needs to know the replay arrived at the same place.
Block numbers are those of a simulated instance and are marked as such wherever they appear. The transitions themselves are produced by the machine.
OPEN THE EXPLORER| BLOCK | CYCLE | PC | OP | OPERANDS | RESULT | COMMITMENT |
|---|---|---|---|---|---|---|
| 21,004,311 | 12,482,187 | 0x000 | LDI | R2, #17 | R2 ← 0x0011 | E3CA559F33AB8CA7… |
| 21,004,312 | 12,482,188 | 0x001 | LDI | R5, #0 | R5 ← 0x0000 | 366186BAF182A65C… |
| 21,004,313 | 12,482,189 | 0x002 | LDI | R1, #0 | R1 ← 0x0000 | 9BD974B7B6A5D135… |
| 21,004,314 | 12,482,190 | 0x003 | STORE | [0x020], R1 | [020] ← 0x0000 | 2A26DAC8CF5D1CBA… |
| 21,004,315 | 12,482,191 | 0x004 | LOAD | R1, [0x020] | R1 ← 0x0000 | 06D5379822C914B3… |
| 21,004,316 | 12,482,192 | 0x005 | ADD | R1, R2 | R1 ← 0x0011 | 37625B2A005E5A49… |
| 21,004,317 | 12,482,193 | 0x006 | STORE | [0x020], R1 | [020] ← 0x0011 | 3816D955D8A9E231… |
| 21,004,318 | 12,482,194 | 0x007 | MOV | R3, R1 | R3 ← 0x0011 | AC9713D0FD2B6B17… |
| 21,004,319 | 12,482,195 | 0x008 | INC | R5 | R5 ← 0x0001 | 164D7806008B14DF… |
| 21,004,320 | 12,482,196 | 0x009 | CMPI | R5, #8 | FLAGS · N · · | 5247ECD78A2E6574… |
| 21,004,321 | 12,482,197 | 0x00A | JNZ | 0x004 | PC ← 0x004 | 4E169C58431A432D… |
| 21,004,322 | 12,482,198 | 0x004 | LOAD | R1, [0x020] | R1 ← 0x0011 | 6924C6CC0A207842… |
| 21,004,323 | 12,482,199 | 0x005 | ADD | R1, R2 | R1 ← 0x0022 | F2145DBEDBB17F78… |
| 21,004,324 | 12,482,200 | 0x006 | STORE | [0x020], R1 | [020] ← 0x0022 | 906179B9709B8BE1… |
| 21,004,325 | 12,482,201 | 0x007 | MOV | R3, R1 | R3 ← 0x0022 | 79066DDED770002B… |
| 21,004,326 | 12,482,202 | 0x008 | INC | R5 | R5 ← 0x0002 | FB011B7A64BE755F… |
| 21,004,327 | 12,482,203 | 0x009 | CMPI | R5, #8 | FLAGS · N · · | DDF234DB65EC4A86… |
| 21,004,328 | 12,482,204 | 0x00A | JNZ | 0x004 | PC ← 0x004 | 821B6064D57FB9ED… |
| 21,004,329 | 12,482,205 | 0x004 | LOAD | R1, [0x020] | R1 ← 0x0022 | D0633D70D6AD8F14… |
| 21,004,330 | 12,482,206 | 0x005 | ADD | R1, R2 | R1 ← 0x0033 | BBA051503D260B5A… |
| 21,004,331 | 12,482,207 | 0x006 | STORE | [0x020], R1 | [020] ← 0x0033 | 21B53B10425FF2C0… |
| 21,004,332 | 12,482,208 | 0x007 | MOV | R3, R1 | R3 ← 0x0033 | 5AC0C48515F93CAA… |
| 21,004,333 | 12,482,209 | 0x008 | INC | R5 | R5 ← 0x0003 | 562DB77307881652… |
| 21,004,334 | 12,482,210 | 0x009 | CMPI | R5, #8 | FLAGS · N · · | 7FCA345247B72865… |
E3CA559F33AB8CA7
This state was not read from a record. The program was replayed from cycle zero to cycle 1 to produce it, on ARRAY-16 R0.
The editor below assembles with the same assembler the reference programs use, and runs on the same machine every other panel on this page is watching. Errors are reported with their line and their reason; a program that assembles will execute.
STEP retires exactly one instruction. RUN supplies edges at the selected rate. RESET returns the machine to cycle zero with a cleared store, which is the only way back: there is no undo, because a state transition is not reversible.
LAUNCH THE APP| ADDR | WORD | DISASSEMBLY | SOURCE |
|---|---|---|---|
| 000 | 0021002A | LDI R1, #42 | LDI R1, #42 |
| 001 | 00220011 | LDI R2, #17 | LDI R2, #17 |
| 002 | 00912000 | ADD R1, R2 | ADD R1, R2 ; R1 ← 0x00 |
| 003 | 00501020 | STORE [0x020], R1 | STORE [0x020], R1 |
| 004 | 00330020 | LOAD R3, [0x020] | LOAD R3, [0x020] |
| 005 | 0183003B | CMPI R3, #59 | CMPI R3, #59 |
| 006 | 01A00008 | JMZ 0x008 | JMZ done |
| 007 | 002400FF | LDI R4, #255 | LDI R4, #0x0FF ; not reach |
| 008 | 01F00000 | HALT | done: HALT |
| # | BLOCK | PC | OP | OPERANDS | RESULT | Φ |
|---|---|---|---|---|---|---|
| NO TRANSITIONS COMMITTED SINCE RESET | ||||||
| NO TRANSITIONS COMMITTED SINCE RESET | ||||||
| NO TRANSITIONS COMMITTED SINCE RESET | ||||||
A processor does not contain time. It contains a state and a rule for producing the next one, and something outside it decides when that happens. In a package on a desk that something is an oscillator. Here it is the chain: the block supplies the edge, and the machine supplies the step.
The consequence is that block resolution is clock resolution. The machine has no notion of being fast or slow, and no operator needs to keep it running. A halted machine is not offline — it is a machine whose sequencer has stopped and whose state is still readable.
Phases are internal. One instruction retires per edge, and the number of phases inside that instruction depends on what it does: 3 for a transfer that resolves in decode, 5 for one that visits the arithmetic unit and writes back.
The state required to reproduce execution, not a description of it: the register file, the store, the pointer, the flags and the counter. A commitment to that state is enough to detect any divergence.
That the successor state offered for a block is the one the architecture defines for the current state. An execution is valid only if the resulting architectural state matches the canonical transition.
Keep it alive. There is no operator, no keeper and no scheduler. If a block is produced, an edge exists; if no block is produced, the machine is exactly where it was.
Each layer below consumes a defined representation and produces the next one. No layer infers anything about the layer above it, and none of them can be skipped: text becomes a canonical word, a word becomes a transition, and a transition becomes a commitment that a block carries.
The trace is not an explanation of execution. It is the execution, written down in the order it happened.
Names in this field usually describe what a system promises. ARRAY describes what the machine is made of.
There is one cell. 9 of it make a full adder, 16 full adders make the adder, and 3,912 make the whole processor. Sixteen registers are 256 instances of the same flip-flop, addressed by index. The store is 4,096 instances of the same byte. The trace is an array of transitions, one per block. Nothing in the machine is a special case, because there is only one kind of part.
That makes the name checkable, which is the only kind of claim this project makes: every figure on the datasheet is a count of something repeated. If any part of the machine needed a second kind of cell, the name would be wrong.