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STRATA
03 · INSTRUCTION SET
5-BIT FIELD · 32 DEFINED · 0 RESERVED

Five bits.
Thirty-two opcodes.

The opcode field is five bits wide, producing thirty-two possible instructions. All thirty-two are defined, so the set is closed: there is no reserved space, no extension mechanism, and no undefined opcode for a program to reach. The architecture is fixed. Programs are data.

Two omissions are deliberate. There is no SWAP, because three exclusive disjunctions exchange two registers without a temporary. There are no input or output instructions, because both ports are mapped into the store and a load already reads.

This is the STRATA-16 R0 architecture specification. It is implemented by the machine in this page and by the independent model used in CHECK 02. It is not a deployed instruction set.

INSTRUCTION WORD32 BIT · 25 SIGNIFICANT
RSV31:257 BITOP24:205 BITRD19:164 BITRS15:124 BITIMM/ADDR11:012 BITMSB 310 LSB

A word is canonical when the seven reserved bits are zero and every field the instruction does not read is zero. Exactly one encoding exists for any instruction, which is what makes one machine’s transition comparable with another’s without a normalisation step. A non-canonical word raises a fault at fetch.

THE SET32 OPCODES
00000
NOP
00001
MOV
00010
LDI
00011
LOAD
00100
LDR
00101
STORE
00110
STR
00111
PUSH
01000
POP
01001
ADD
01010
ADDI
01011
SUB
01100
SUBI
01101
INC
01110
DEC
01111
NEG
10000
AND
10001
OR
10010
XOR
10011
NOT
10100
SHL
10101
SHR
10110
ASR
10111
CMP
11000
CMPI
11001
JMP
11010
JMZ
11011
JNZ
11100
JMN
11101
CALL
11110
RET
11111
HALT
TRANSFER
2
MEMORY
4
STACK
2
ARITHMETIC
7
LOGIC
4
SHIFT
3
COMPARE
2
CONTROL
8
OPCODE EXPLORERSELECT AN INSTRUCTION
CLASS
32 OF 32
OPCODEHEXMNEMONICOPERANDSFLAGSΦ
0000000——3
0000101Rd, Rs—4
0001002Rd, #imm—4
0001103Rd, [addr]—5
0010004Rd, [Rs]—5
0010105[addr], Rs—5
0011006[Rd], Rs—5
0011107Rs—5
0100008Rd—5
0100109Rd, RsZNCV5
010100ARd, #immZNCV5
010110BRd, RsZNCV5
011000CRd, #immZNCV5
011010DRdZNCV5
011100ERdZNCV5
011110FRdZNCV5
1000010Rd, RsZN5
1000111Rd, RsZN5
1001012Rd, RsZN5
1001113RdZN5
1010014Rd, #nZNC5
1010115Rd, #nZNC5
1011016Rd, #nZNC5
1011117Rd, RsZNCV5
1100018Rd, #immZNCV5
1100119addr—5
110101Aaddr—5
110111Baddr—5
111001Caddr—5
111011Daddr—5
111101E——5
111111F——3
INSTRUCTION · ARITHMETICOPCODE 01001

ADDRd, Rs

00912000 · ADD R1, R2

Adds the source register to the destination register.

ENCODING · EXAMPLE WORDRSV31:257 BITOP24:205 BITRD19:164 BITRS15:124 BITIMM/ADDR11:012 BITMSB 310 LSB0x00912000
FIELDS READ
  • RDR1
  • RSR2
  • IMM/ADDRzero
  • RSV 31:25must be zero
PHASES
  • FETCHRUNS
  • DECODERUNS
  • EXECUTERUNS
  • WRITEBACKRUNS
  • COMMITRUNS

5 PHASES

FLAGS WRITTEN
ZNCV

UNLISTED FLAGS RETAIN THEIR VALUE

CONTROL ASSERTIONS · 7/15
IR_LDPC_INCPC_LOADRARBIMM_SELALU_ENSH_ENFLG_WRREG_WRMEM_RDMEM_WRSP_DECSP_INCHALT_L
INSTRUCTION SET32 OPCODES · 5-BIT FIELD
OPCODEMNEMONICOPERANDSCLASSFLAGSΦDESCRIPTION
00000NOP—CONTROL—3No architectural state changes except the program counter.
00001MOVRd, RsTRANSFER—4Copies the source register into the destination register.
00010LDIRd, #immTRANSFER—4Loads a zero-extended twelve-bit immediate into the destination register.
00011LOADRd, [addr]MEMORY—5Reads a sixteen-bit word from an absolute RAM address into the destination register.
00100LDRRd, [Rs]MEMORY—5Reads a word from the RAM address held in the source register.
00101STORE[addr], RsMEMORY—5Writes the source register to an absolute RAM address.
00110STR[Rd], RsMEMORY—5Writes the source register to the RAM address held in the destination register.
00111PUSHRsSTACK—5Decrements the stack pointer and writes the source register to the stack page.
01000POPRdSTACK—5Reads a word from the stack page into the destination register and increments the stack pointer.
01001ADDRd, RsARITHMETICZNCV5Adds the source register to the destination register.
01010ADDIRd, #immARITHMETICZNCV5Adds a zero-extended twelve-bit immediate to the destination register.
01011SUBRd, RsARITHMETICZNCV5Subtracts the source register from the destination register.
01100SUBIRd, #immARITHMETICZNCV5Subtracts a zero-extended twelve-bit immediate from the destination register.
01101INCRdARITHMETICZNCV5Adds one to the destination register.
01110DECRdARITHMETICZNCV5Subtracts one from the destination register.
01111NEGRdARITHMETICZNCV5Replaces the destination register with its two's complement.
10000ANDRd, RsLOGICZN5Bitwise conjunction of the destination and source registers.
10001ORRd, RsLOGICZN5Bitwise disjunction of the destination and source registers.
10010XORRd, RsLOGICZN5Bitwise exclusive disjunction of the destination and source registers.
10011NOTRdLOGICZN5Bitwise complement of the destination register.
10100SHLRd, #nSHIFTZNC5Shifts the destination register left by a four-bit distance. The last bit shifted out enters carry.
10101SHRRd, #nSHIFTZNC5Logical right shift. Vacated bits are filled with zero.
10110ASRRd, #nSHIFTZNC5Arithmetic right shift. Vacated bits are filled with the sign bit.
10111CMPRd, RsCOMPAREZNCV5Subtracts the source from the destination, writing flags and discarding the result.
11000CMPIRd, #immCOMPAREZNCV5Compares the destination register against a twelve-bit immediate.
11001JMPaddrCONTROL—5Unconditional transfer of control to a ROM address.
11010JMZaddrCONTROL—5Transfers control if the zero flag is set.
11011JNZaddrCONTROL—5Transfers control if the zero flag is clear.
11100JMNaddrCONTROL—5Transfers control if the negative flag is set.
11101CALLaddrCONTROL—5Pushes the return address onto the stack page and transfers control.
11110RET—CONTROL—5Pops a return address from the stack page into the program counter.
11111HALT—CONTROL—3Stops the sequencer. The architectural state is retained and remains readable.
07 · THE INSTRUMENT
32 OPCODES · 2,048 WORDS OF ROM

Write to it.
Step it.

The editor below assembles with the same assembler the reference programs use, and runs on the same machine every other panel on this page is watching. Errors are reported with their line and their reason; a program that assembles will execute.

STEP retires exactly one instruction. RUN supplies edges at the selected rate. RESET returns the machine to cycle zero with a cleared store, which is the only way back: there is no undo, because a state transition is not reversible.

// PROGRAM
ASSEMBLED · NOT LOADED
CODE15 LINES · 9 WORDS
36 BYTES
BYTECODEDIGEST 6DDCC5534BB8…
ADDRWORDDISASSEMBLY
0000021002ALDI R1, #42
00100220011LDI R2, #17
00200912000ADD R1, R2
00300501020STORE [0x020], R1
00400330020LOAD R3, [0x020]
0050183003BCMPI R3, #59
00601A00008JMZ 0x008
007002400FFLDI R4, #255
00801F00000HALT
SYMBOLS
done = 0x008 · 1 REF
STATEIDLE
PC0x000
IR0x00000000
SP0x0080
CYCLE12,482,186
FLAGSZNCV
FETCH
DECODE
EXECUTE
WRITEBACK
COMMIT
REGISTER FILE16 × 16 · CYCLE 0
R00000
R10000
R20000
R30000
R40000
R50000
R60000
R70000
R80000
R90000
RA0000
RB0000
RC0000
RD0000
RE0000
RF0000
TRACENEWEST FIRST
#BLOCKPCOPOPERANDSRESULT
NO TRANSITIONS COMMITTED SINCE RESET
NO TRANSITIONS COMMITTED SINCE RESET
NO TRANSITIONS COMMITTED SINCE RESET
REFERENCE PROGRAMS6 PROGRAMS · ASSEMBLED AT BUILD
PROGRAMCLOCKEXERCISESNOTE
ACCUMULATECONTINUOUSMEMORY · ARITHMETIC · COMPARE · BRANCHReads a word from RAM, adds a constant, writes it back, and repeats. The canonical resident program.
DECIDECONTINUOUSPORT IN · PORT OUT · COMPARE · BRANCHClassifies the input port into three bands and drives the output port. One decision per pass.
MULTIPLYHALTSCALL · RET · SHIFT · LOGIC · STACKShift and add multiplication in a subroutine. There is no multiplier in the netlist.
SEQUENCEHALTSREGISTER INDIRECT · MEMORY · ARITHMETICWrites sixteen words of an additive sequence through a register pointer.
STACK WALKHALTSPUSH · POP · CALL · RETExercises the stack page and one level of call depth.
ECHOCONTINUOUSPORT IN · PORT OUT · SHIFTDoubles the input port into the output port. The boundary is one byte wide in each direction.