From one primitive
to blockspace.
Every part of the machine is built from a single computational primitive. Nothing is assumed and nothing is hidden: the processor is constructed in layers, from boolean logic to a verifiable state machine, and each layer is countable in terms of the layer below it.
NAND is universal, so no second kind of gate is required anywhere above it. The cost of that decision is visible in the budget: two read ports account for 1,920 of the 3,912 cells, because a sixteen-to-one multiplexer is expensive when it is made of nothing but NAND.
One two-input cell whose output is low only when both inputs are high. Every gate in the machine — inverter, conjunction, disjunction, exclusive disjunction, multiplexer, latch — is composed from it.
Sixteen full adders in a ripple carry chain. The carry out of bit fifteen is the carry flag; overflow is that carry differing from the carry into bit fifteen. Both flags come off the chain, not out of a formula.
The processor layer is the whole netlist, not a block of its own. Sequential elements are counted separately because a flip-flop is not a gate: it is a state element built from gates that holds a value between two edges of an external clock.
| BLOCK | LAYER | NAND | FF | BUDGET | DERIVATION |
|---|---|---|---|---|---|
| ADDER | ARITHMETIC | 144 | — | 16 × full adder (9) | |
| LOGIC UNIT | ARITHMETIC | 160 | — | 16 × (AND 2 + OR 3 + XOR 4 + NOT 1) | |
| BARREL SHIFTER | ARITHMETIC | 256 | — | 4 stages × 16 × MUX2 (4) | |
| RESULT SELECT | ARITHMETIC | 192 | — | 16 × 4→1 MUX (3 × MUX2) | |
| FLAG UNIT | ARITHMETIC | 52 | 4 | Z: 15 × OR (3) + NOT (1) = 46 · N C V: 6 · 4 flip-flops | |
| READ PORT A | REGISTERS | 960 | — | 16 × 16→1 MUX (15 × MUX2 = 60) | |
| READ PORT B | REGISTERS | 960 | — | 16 × 16→1 MUX (15 × MUX2 = 60) | |
| REGISTER FILE | REGISTERS | 132 | 256 | 16 × AND4 (6) + 4 × NOT + 16 × AND2 (2) · 16 × 16 flip-flops | |
| COUNTER INCREMENT | CONTROL | 72 | 12 | 12 × half adder (6) · 12 flip-flops | |
| COUNTER SOURCE | CONTROL | 96 | — | 2 × (12 × MUX2) | |
| OPCODE DECODER | CONTROL | 261 | — | 32 × AND5 (8) + 5 × NOT | |
| MEMORY PORT | MEMORY | 242 | — | address 3→1 MUX 96 · word assembly 64 · port compare 82 | |
| STACK POINTER | MEMORY | 80 | 8 | 8 × half adder (6) + 8 × MUX2 · 8 flip-flops | |
| INSTRUCTION REGISTER | CONTROL | 64 | 32 | 32 × AND2 (2) load enable · 32 flip-flops | |
| CONTROL MATRIX | CONTROL | 241 | — | 24 control terms × 3 × OR (3) = 216 · 5 phase lines × AND2 = 10 · 15 glue |
Every row is arithmetic. If a derivation and its figure disagree, the datasheet is wrong: the totals printed anywhere on this site are the sum of this table, and the self-test refuses to pass if the flip-flop budget and the state element budget differ.